CV

Education

B.S. Nanjing University, 2013.09-2017.06
M.S. Nanjing University, 2017.09-2020.06
- Supervisor: Zhongfeng Wang (Professor of Nanjing University and Sun Yat-sen University, Fellow of IEEE)
Ph.D. Shanghai Jiao Tong University, 2021.04-2025.03 (expected)
- Supervisor: Guanghui He (Cheung Kong Professor of Shanghai Jiao Tong University), and Ningyi Xu (Professor of Shanghai Jiao Tong University )

In general, I’m interested in hardware architecture design for domain-specific computing.

Error correction codes and their hardware architecture design (previous)
I have a certain research background in both LDPC codes and polar codes. I specialized in algebraic codes, such as RS codes, BCH codes, and their concatenated codes.
Stochastic computing (previous)
As a new computing paradigm, stochastic computing has its advantages when compared with conventional binary computing, with low-complexity arithmetic units and fault tolerance being the most prominent ones.
Hardware acceleration for deep learning (current)
Related topics include quantization, arithmetic units, accelerator hardware architectures, and more. The involved models encompass convolutional convolutional neural networks (CNNs), Transformers, and large language models (LLMs).

Reviewer for IEEE Communications Letters, IEEE Transactions on Circuits and Systems II: Express Briefs, Science China: Information Science, and IEEE Access.